Generally, a clock frequency divider is constructed by two serial D flip-flops. FIG. 1 is a schematic diagram of a conventional clock frequency divider 10 comprising a first D flip-flop 12 and a second D flip-flop 14. The first flip-flop 12 has a positive-phase data output end coupled to a positive-phase data input end of the second D flip-flop 14, and a negative-phase data output end coupled to a negative-phase data input end of the second D flip-flop 14. The second D flip-flop 14 has a positive-phase data output end coupled to a negative-phase data input end of the first flip-flop 12, and a negative-phase data output end coupled to a positive-phase data input end of the first flip-flop 12. In addition, the first D flip-flop 12 and the second D flip-flop 14 are controlled by a differential pair of input clocks clk and clkb. The first input clock clk is coupled to a sampling control end of the first D flip-flop 12 and a latch control end of the second D flip-flop 14, and the second input clock clkb is coupled to a latch control end of the first D flip-flop 12 and a sampling control end of the second D flip-flop 14. Therefore, the clock frequency divider 10 divides by the differential pair of input clocks clk and clkb to generate four frequency-divided output clocks clk1, clk2, clk3 and clk4 having phases differences of 90 degrees, e.g., phases of the output clocks clk1, clk2, clk3 and clk4 are respectively 0 degree, 90 degrees, 180 degrees and 270 degrees.
As mentioned above, since the conventional clock frequency divider generates four output clocks having different phases according to two input clocks, when two conventional frequency dividers are coupled in series to perform a divide-by-four calculation, a second-stage frequency divider only receives two output clocks of the four output clocks outputted by a first-stage frequency divider. In other words, load conditions of four output ends of the first-stage frequency divider are not completely identical, so that errors occur in the phases of the four output clocks generated by the first-stage frequency divider. Accordingly, when an operating circuit, e.g., a modulator circuit, performs modulation/demodulation on a data signal via the foregoing four output clocks having phase errors (i.e., the four output clocks generated by the first-stage frequency divider), serious errors may occur in a modulated/demodulated data. Therefore, a solution for frequency dividing a group of clock signals while maintaining accurate phases is in need.